1. Field of the Invention
The invention relates to a method for manufacturing a multi-gate transistor device, and more particularly, to a method for manufacturing a multi-gate transistor device having raised source/drain.
2. Description of the Prior Art
Conventional planar metal-oxide-semiconductor (MOS) transistor has difficulty when scaling to 65 nm and below. Therefore the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor.
Please refer to FIG. 1, which is a schematic drawing of a conventional FinFET device. As shown in FIG. 1, the conventional FinFET device 100 is formed by: firstly a single crystalline silicon layer of a silicon-on-insulator (SOI) substrate 102 is patterned to form a fin film (not shown) in the SOI substrate 102 by proper etching process. Then, a high-K insulating layer 104 covering the fin film is formed and followed by forming a gate 106 covering the high-K insulating layer 104 and the fin film. Next, ion implantation and anneal treatment are performed to form a source/drain 108 in the fin film not covered by the gate 106. Since the manufacturing processes of the FinFET device are easily integrated into the traditional logic device processes, it provides superior compatibility. Furthermore, due to the structural particularity of its three-dimensional structure, traditional shallow trench isolation (STI) is not required in FinFET technology. More important, since the FinFET device increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. In addition, the channel region is longer under the same gate length, and thus the current between the source and the drain is increased.
It is well-known to those skilled in the art that since the source/drain 108 of the FinFET device 100 are still formed by ion implantation, it is unavoidable to damage the lattice of the fin film. State-of-the-art may repair this damage by providing high temperature in the following anneal process. However, the temperature sufficient to repair such damage caused by the ion implantation undesirably deteriorates the stability of the high-K insulating layer 104. In other words, due to the low thermal budget of the high-K insulating layer 104, damage caused by the ion implantation cannot be repaired. Consequently, a method that is capable of overcoming the abovementioned unsatisfactorily dilemmatic problem is stilled in need.